product brief april 1999 orca ? series 3c and 3t field-programmable gate arrays features n high-performance, cost-effective, 0.35 m and 0.3 m 4-level metal technology (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 m). n same basic architecture as lower-voltage, advanced process technology series 3 architecture (see orca series 3lxxxb fpgas documentation). n up to 186,000 usable system gates. n up to 452 user i/os. (or3txxx i/os are 5 v tolerant to allow interconnection to both 3.3 v and 5 v devices, selectable on a per-pin basis.) n pin-selectable i/o clamping diodes provide 5 v or 3.3 v pci compliance and 5 v tolerance on or3txxx devices. n twin-quad programmable function unit (pfu) architec- ture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. n nine user registers per pfu, one following each lut, plus one extra. all have programmable clock enable and local set/reset, plus a global set/reset that can be dis- abled per pfu. n flexible input structure (fins) of the pfus provides a routability enhancement for luts with shared inputs and the logic flexibility of luts with independent inputs. n fast-carry logic and routing to adjacent pfus for nibble-, byte-wide, or longer arithmetic functions, with the new option to register the pfu carry-out. n softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu for up to 40% speed improvement. n supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each programmable logic cell (plc), with over 50% speed improvement typical. n abundant hierarchical routing resources based on rout- ing two data nibbles and two control lines per set provide for faster place and route implementations and less rout- ing delay. n ttl or cmos input levels programmable per pin for the or3cxxx (5.0 v) devices. n individually programmable drive capability: 12 ma sink/ 6 ma source or 6 ma sink/3 ma source. n built-in boundary scan ( ieee ? 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. n enhanced system clock routing for low-skew, high-speed clocks originating on-chip or at any i/o. n up to four expressclk inputs allow extremely fast clock- ing of signals on- and off-chip plus access to internal general clock routing. n stopclk feature to glitchlessly stop/start the express- clks independently by user command. n programmable i/o (pio) has: fast-capture input latch and input flip-flop (ff)/latch for reduced input setup time and zero hold time. capability to (de)multiplex i/o signals. fast access to slic for decodes and pa l -like func- tions. output ff and two-signal function generator to reduce clk to output propagation delay. fast open-drain drive capability. capability to register 3-state enable signal. n baseline fpga family used in series 3+ fpscs (field- programmable system chips) which combine fpga logic and standard-cell logic on one device. * pa l is a trademark of advanced micro devices, inc. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. table 1. lucent technologies orca series 3c and 3t fpgas ? the system gate counts range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu) , and 12 gates per slic/ff pair (one per pfu). each of the four pios per pic is counted as 16 gates (three ffs, fast-capture latch, o utput logic, clk, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram ( or 512 gates) per pfu. device system gates ? luts registers max user ram user i/os array size process technology or3t20 36k 1152 1872 18k 196 12 x 12 0.3 m/4 lm or3t30 48k 1568 2436 25k 228 14 x 14 0.3 m/4 lm or3c/3t55 80k 2592 3780 42k 292 18 x 18 0.3 m/4 lm or3c/3t80 116k 3872 5412 62k 356 22 x 22 0.3 m/4 lm or3t125 186k 6272 8400 100k 452 28 x 28 0.3 m/4 lm
preliminary product brief orca series 3 fpgas april 1999 2 lucent technologies inc. system-level features system-level features reduce glue logic requirements and make a system on a chip possible. these features in the orca or3c/txxx include: n full pci local bus compliance. n dual-use microprocessor interface (mpi) can be used for configuration, readback, device control, and device status, as well as for a general-purpose inter- face to the fpga. glueless interface to i960 * and powerpc ? processors with user-configurable address space provided. n parallel readback of configuration data capability with the built-in microprocessor interface. n programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be combined with fpga logic to create complex functions, such as dig- ital phase-locked loops (dpll), frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per device. n true, internal, 3-state, bidirectional buses with simple control provided by the slic. n 32 x 4 ram per pfu, configurable as single- or dual- port at >183 mhz (-7 speed). create large, fast ram/ rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. * i960 is a registered trademark of intel corporation. ? powerpc is a registered trademark of international business machines corporation. 1. implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output. 2. implemented using two 32 x 4 rams and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output. 3. implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 pfus contain only pip elining registers). 4. implemented using 32 x 4 ram mode with read data on 3-state buffer to bidirectional read/write bus. 5. implemented using 32 x 4 dual-port ram mode. 6. implemented in one partially occupied slic with decoded output set up to ce in same plc. 7. implemented in five partially occupied slics. table 2. orca or3c/txxx system performance parameter # pfus speed unit -4 -5 -6 -7 16-bit loadable up/down counter 2 76 99 128 161 mhz 16-bit accumulator 2 76 99 128 161 mhz 8 x 8 parallel multiplier: multiplier mode, unpipelined 1 rom mode, unpipelined 2 multiplier mode, pipelined 3 11.5 8 15 19 50 74 24 65 101 30 79 123 37 99 159 mhz mhz mhz 32 x 16 ram (synchronous): single-port, 3-state bus 4 dual-port 5 4 4 94 122 122 158 147 195 183 237 mhz mhz 128 x 8 ram (synchronous): single-port, 3-state bus 4 dual-port 5 8 8 86 86 112 112 135 135 168 168 mhz mhz 8-bit address decode (internal): using softwired luts using slics 6 0.25 0 4.87 2.35 3.66 1.82 2.58 1.23 2.03 0.99 ns ns 32-bit address decode (internal): using softwired luts using slics 7 2 0 16.06 6.91 12.07 5.41 9.01 4.21 7.03 3.37 ns ns 36-bit parity check (internal) 2 16.06 12.07 9.01 7.03 ns
lucent technologies inc. 3 preliminary product brief april 1999 orca series 3 fpgas support n orca foundry development system support. n supported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis. description fpga overview the orca series 3 fpgas are a new generation of sram-based fpgas built on the successful or2c/ txxa fpga (series 2) from lucent technologies microelectronics group, with enhancements and inno- vations geared toward todays high-speed designs and tomorrows systems on a single chip. designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the orca series 2 devices, the series 3 family more than doubles the logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 3 devices contain many new patented enhancements and are offered in a vari- ety of packages, speed grades, and temperature ranges. the orca series 3 fpgas consist of three basic ele- ments: programmable logic cells (plcs), programma- ble input/output cells (pics), and system-level features. an array of plcs is surrounded by pics. each plc contains a programmable function unit (pfu), a sup- plemental logic and interconnect cell (slic), local rout- ing resources, and configuration ram. most of the fpga logic is performed in the pfu (see figure 1), but decoders, pa l -like functions, and 3-state buffering can be performed in the slic (see figure 2). the pics pro- vide device inputs and outputs and can be used to reg- ister signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals (see figure 3). some of the system-level functions include the new microprocessor interface (mpi) and the programmable clock manager (pcm). plc logic each pfu within a plc contains eight 4-input (16-bit) look-up tables (luts), eight latches/flip-flops (ffs), and one additional flip-flop that may be used indepen- dently or with arithmetic functions. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. luts may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected to plc routing resources and to the outputs of the pfu. it contains 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3-state drivers in the slic and their direct connections to the pfu outputs make fast, true 3-state buses possible within the fpga, reducing required routing and allowing for real-world system performance. pic logic the or3c/txxx pic addresses the demand for ever- increasing system clock speeds. each pic contains four programmable inputs/outputs (pios) and routing resources. on the input side, each pio contains a fast- capture latch that is clocked by an expressclk. this latch is followed by a latch/ff that is clocked by a sys- tem clock from the internal general clock routing. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. two input signals are available to the plc array from each pio, and the orca series 2 capability to use any input pin as a clock or other global input is maintained. on the output side of each pio, two outputs from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the i/o buffer associated with each pad is very similar to the orca series 2 buffer with a new, fast, open-drain option for ease of use on system buses. the output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. in addition, this 3-state signal can be regis- tered or nonregistered.
preliminary product brief orca series 3 fpgas april 1999 4 lucent technologies inc. description (continued) note: all multiplexers without select inputs are configuration selector multiplexers. figure 1. simplified pfu diagram 5-5743 sel cin d ce ck s/r ff8 regcout cout 1 aswe lsr k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 f5d k7_0 k7_1 k7_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5c clk a b c d a b c d a b c d k4 k5 k6 k7 din7 din6 din5 din4 reg5 d0 d1 ce ck s/r dsel q5 f5 reg6 d0 d1 ce ck s/r dsel q6 f6 reg7 d0 d1 ce ck s/r dsel q7 f7 reg4 d0 d1 ce ck s/r dsel q4 f4 a b c d f5mode45 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 f5b k3_0 k3_1 k3_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5a a b c d a b c d a b c d k0 k1 k2 k3 din3 din2 din1 din0 reg1 d0 d1 ce ck s/r dsel q1 f1 reg2 d0 d1 ce ck s/r dsel q2 f2 reg3 d0 d1 ce ck s/r dsel q3 f3 reg0 d0 d1 ce ck s/r dsel q0 f0 a b c d f5mode01 f5mode67 f5mode23 0 0 0 0 0 0 0 0 0 0 0 0 ce 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0
preliminary product brief april 1999 orca series 3 fpgas lucent technologies inc. 5 description (continued) 5-5744(f) figure 2. slic diagram (all modes) bri9 i9 bli9 bri8 i8 bli8 bri7 i7 bli7 bri6 i6 bli6 bri5 i5 bli5 bri4 i4 bli4 bri3 i3 bli3 bri2 i2 bli2 bri1 i1 bli1 bri0 i0 bli0 bl09 br09 bl08 br08 bl07 br07 bl06 br06 bl05 br05 bl04 br04 bl03 br03 bl02 br02 bl01 br01 bl00 br00 dec dec 0/1 0/1 tri 0/1 0/1 high z when low
preliminary product brief orca series 3 fpgas april 1999 6 lucent technologies inc. description (continued) system features the series 3 also provides system-level functionality by means of its dual-use microprocessor interface (mpi) and its innovative programmable clock manager (pcm). these functional blocks allow for easy glueless system interfacing and the capability to adjust to vary- ing conditions in todays high-speed systems. the mpi provides a glueless interface between the fpga and powerpc and i960 microprocessors. it can be used for configuration and readback, as well as for monitoring fpga status. the mpi also provides a gen- eral-purpose microprocessor interface to the fpga user-defined logic following configuration. two pcms are provided on each series 3 device. each pcm can be used to manipulate the frequency, phase, and duty cycle of a clock signal. clocks may be input from the dedicated corner expressclk input (in the same corner as the pcm block) or from general rout- ing. output clocks from the pcm can be sent to the system clock spines and/or to the expressclk and fast clock spines on the edges of the device adjacent to the pcm. expressclk/fast clock and system clock output frequencies can differ by up to a factor of 8 to allow slow i/o clocking with fast internal processing (or vice versa). each pcm is capable of manipulating clocks from 5 mhz to 120 mhz. frequencies can be adjusted from 1/8x to 64x the input clock frequency, and duty cycles and phase delays can be adjusted from 3.125% to 96.875%. routing the abundant routing resources of the series 3 fpgas are organized to route signals individually or as buses with related control signals. clocks are routed on a low- skew, high-speed distribution network and may be sourced from plc logic, externally from any i/o pad, or from the very fast expressclk pins. expressclks may be glitchlessly and independently enabled and disabled with a programmable control signal using the new stopclk feature. the improved pic routing resources are now similar to the patented intra-plc routing resources and provide great flexibility in moving signals to and from the pios. this flexibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to spe- cific pins. configuration the fpgas functionality is determined by internal con- figuration ram. the fpgas internal initialization/con- figuration circuitry loads the configuration data at powerup or under system control. the ram is loaded by using one of several configuration modes. the con- figuration data resides externally in an eeprom or any other storage media. serial eeproms provide a sim- ple, low pin count method for configuring fpgas. a new, easy method for configuring the devices is through the microprocessor interface. 5-5805(f).c figure 3. series 3 programmable input/output (pio) image from orca foundry in2 in1 d0 d1 ck sp sd lsr inregmode latchff latch ff d ck normal inverted reset set level mode ttl cmos up down none pull-mode buffer ts fast slew sink reset set lsr sp ck d out1 out2 eclk sclk ce ce_over_lsr lsr_over_ce async lsr enable_gsr disable_gsr out1outreg out2outreg out1out2 nor xor xnor and nand or pio logic clkin 0 0 1 0 pad q q 1 pd to routing q 1 eclk sclk pmux from routing mode lsr ck d0 q
lucent technologies inc. 7 preliminary product brief april 1999 orca series 3 fpgas description (continued) orca foundry development system the orca foundry development system is used to process a design from a netlist to a configured fpga. this system is used to map a design onto the orca architecture and then place and route it using orca foundrys timing-driven tools. the development system also includes interfaces to, and libraries for, other popu- lar cae tools for design entry, synthesis, simulation, and timing analysis. the orca foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured fpga. in the design flow, the user defines the functionality of the fpga at two points in the design flow: at design entry and at the bit stream generation stage. following design entry, the development systems map, place, and route tools translate the netlist into a routed fpga. a static timing analysis tool is provided to deter- mine device speed and a back-annotated netlist can be created to allow simulation. timing and simulation output files from orca foundry are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the configuration data which is loaded into the fpgas internal configuration ram. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, orca foundry pro- duces configuration data that implements the various logic and routing options discussed in this product brief. additional information contact your local lucent technologies representative for additional information regarding the orca series 3 fpga devices, or visit our website at http://www.lucent.com/orca
for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. copyright ? 1999 lucent technologies inc. all rights reserved april 1999 pn99-058fpga (replaces pn98-012fpga) preliminary product brief orca series 3 fpgas april 1999 ordering information or3c80, -4 speed grade, 240-pin power quad shrink flat package (sqfp2), commercial temperature. or3c80-4 ps 240 device type speed grade package type number of pins temperature range example: table 3. voltage options table 4. temperature options table 5. package options table 6. speed grade options device voltage or3cxx 5.0 v or3txxx 3.3 v symbol description temperature (blank) commercial 0 c to 70 c i industrial C40 c to +85 c symbol description ba plastic ball grid array (pbga) bc enhanced ball grid array (ebga) ps power quad shrink flat package (sqfp2) s shrink quad flat package (sqfp) device speed grade or3cxx -4, -5 or3txxx -5, -6, -7 table 7. orca series 3 package matrix note: c = commercial, i = industrial. packages 208-pin eiaj sqfp 208-pin eiaj/sqfp2 240-pin eiaj sqfp 240-pin eiaj/sqfp2 256-pin pbga 352-pin pbga 432-pin ebga 600-pin ebga s208 ps208 s240 ps240 ba256 ba352 bc432 bc600 or3t20 cl ci ci ci or3t30 ci ci ci ci or3c/t55 ci ci ci ci or3c/t80 ci ci ci ci or3t125 ci ci cici ci
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